h anbit h m n128 8 j url: www.hbe.co.kr 1 hanbit electronics co.,ltd. re v.0.0 (february/ 2002) general description the h m n128 8 j nonvolatile sram is a 1, 048,576 - bit static ram organized as 131,072 byte s by 8 bits. the h m n128 8 j has a self - contained lithium energy source provide reliable non - volatility coupled with the unlimited write cycles of standard sram and integral control circuitry which constantly monitors the single 5v supply for an out - of - tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after v cc ret urns valid and write protection is unconditionally enabled to prevent garbled data. in addition the sram is unconditionally write - protected to prevent an inadvertent write operation. at this time the integral energy source is switched on to sustain the mem ory until after v cc returns valid. the h m n128 8 j uses extremely low standby current cmos sram s, coupled with small lithium coin cells to provide non - volatility without long write - cycle times and the write - cycle limitations associated with eeprom. featu res w access time : 55, 70 ns w high - density design : 4mbit design w battery internally isolated until power is applied w industry - standard 34 - pin 128k x 8 pinout w unlimited write cycles w data retention in the absence of v cc w 10 - years minimum d ata retention in absence of power w automatic write - protection during power - up/power - down cycles w data is automatically protected during power loss w conventional sram operation; unlimited write cycles options marking w timing 55 ns - 55 70 ns - 70 non - volatile sram module 1mbit ( 128 k x 8 - bit) ,34pin - jlcc, 5v part no. hmn 1 2 88j pin assignment jlcc top view 31 30 29 28 27 26 25 24 23 22 21 20 19 18 34 33 32 3 4 1 2 5 6 7 8 9 10 11 12 13 14 15 16 17 a(0) a(1) a(2) a(3) a(4) a(5) a(6) a(7) a(8) a(9) a(10) a(11) a(12) a(13) a(14) nc nc a(15) a(16) d(0) d(1) d(2) d(3) d(4) d(5) d(6) d(7) /ce /oe /we /nbw /rst vcc vss
h anbit h m n128 8 j url: www.hbe.co.kr 2 hanbit electronics co.,ltd. re v.0.0 (february/ 2002) functional descripti on the h m n128 8 j executes a read cycle whenever /we is inactive(high) and /ce is active(low). the address specified by the ad dress inputs(a 0 - a 16 ) defines which of the 131,072 bytes of data is accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable. when power is valid, the h m n128 8 j operates as a standard cmos sram. during power - down and power - up cycles, the h m n128 8 j acts as a nonvolatile memory, automatically protecting and preserving the memory contents. the h m n128 8 j is in the write mode whenever the /we and /ce signals are in the active (l ow) state after address inputs are stable. the later occurring falling edge of /ce or /we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of /ce or /we. all address inputs must be kept valid throughou t the write cycle. /we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the /oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output bus been enabled (/ce and /oe active) then /we will disable the outputs in t odw from its falling edge. the h m n128 8 j provides full functional capability for v cc greater than 4. 75 v and write protects by 4.5 v nominal. power - down/power - up control circuitry constantl y monitors the v cc supply for a power - fail - detect threshold v pfd . when v cc falls below the v pfd threshold, the sram automatically write - protects the data. all inputs to the ram become don t care and all outputs are high impedance. as v cc falls below a pproximately 2. 7 v, the power switching circuit connects the lithium energy soure to ram to retain data. during power - up, when v cc rises above approximately 2. 7 volts, the power switching circuit connects external v cc to the ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 4. 75 volts. block diagram pin description a 0 - a 1 6 : address input /ce : chip enable v ss : ground dq 0 - dq 7 : data in / data out /we : write e nable /oe : output enable v cc : power (+5v) nc : no connection /ce /reset vout /oe /we a(0:16) dq(0:7) vcc vcc /ce2 /ce1 /ce_con
h anbit h m n128 8 j url: www.hbe.co.kr 3 hanbit electronics co.,ltd. re v.0.0 (february/ 2002) truth table mode /oe /ce /we i/o operation power not selected x h x high z standby output disable h l h high z active read l l h d out active write x l l d in active absolute maximum rat ings parameter symbol rating conditions dc voltage applied on v cc relative to v ss v cc - 0.3v to 7.0 dc voltage applied on any pin excluding v cc relative to v ss v t - 0.3v to vcc+0.3 v t v cc +0.3 operating temperature t opr 0 to 70 c storage temperature t stg - 55 c to 125 c soldering temperature t solder 260 c for 10 second note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the recommended dc operating conditions detailed in this data sheet. exposure to higher than recommended voltage for extended periods of time could affect device reliability. recommended dc opera ting conditions ( t a = t opr ) parameter symbol min typical max supply voltage v cc 4.5v - 5.5v ground v ss 0 0 0 input high voltage v ih 2.0 - v cc + 0.3 input low voltage v il - 0.3 - 0.8v note: typical values indicate operation at t a = 25 capacitance (t a =25 , f=1mhz, v cc =5v) description conditions symbol max mi n unit input capacitance input voltage = 0v c in 8 - pf input/output capacitance output voltage = 0v c i/o 10 - pf
h anbit h m n128 8 j url: www.hbe.co.kr 4 hanbit electronics co.,ltd. re v.0.0 (february/ 2002) dc electrical charac teristics (t a = t opr , v ccmin v cc v ccmax ) parameter conditions symbol min typ . max unit input leakage current v in =v ss to v cc i li - - 2.0 m a output leakage current /ce=v ih or /oe=v ih or /we=v il i lo - - 2.0 m a output high voltage i oh = - 1.0ma v oh 2.4 - - v output low voltage i ol = 2.0ma v ol - - 0.4 v v cc trip point (tol=gnd) v cctp 4.5 4.62 4.75 v standby supply current /ce=2.2v i sb - - 3 ma standby supply current /ce v cc - 0.3v, i sb1 - - 150 m a operating power supply current /ce=v il , i i/o =0 ? , v in = v il or v ih , read i cc - - 12 ma v c c / v bat switch point v sw 2.6 2.7 2.8 v note: typical values indicate operation at t a = 25 . characteristics (test conditions) includ ing scope and jig capacitance read cycle (t a = t opr , v ccmin v cc v ccmax ) - 55 - 70 parameter symbol conditions min max min max un i t read cycle time t rc 55 - 70 - ns address access time t acc output load a - 55 - 70 ns chip enable access time t ace output load a 55 - 70 ns output enable to output valid t oe output load a - 25 - 35 ns chip enable to output in low z t clz output load b 10 - 10 - ns output enable to output in low z t olz output load b 5 - 5 - ns chip disable to output in high z t chz output load b 0 20 0 25 ns output disable to output high z t ohz output load b 0 20 0 25 ns output hold from address change t oh output load a 10 - 10 - ns parameter value input pulse levels 0 .8 to 2.4v input rise and fall times 5 ns input and output timing reference levels 1.5v ( unless otherwise specified) output load ( cl 1) = 50 pf+1ttl ) ( cl 1) = 100 pf+1ttl ) see figures cl 1)
h anbit h m n128 8 j url: www.hbe.co.kr 5 hanbit electronics co.,ltd. re v.0.0 (february/ 2002) write cycle (t a = t opr , v ccmin v cc v ccmax ) - 70 - 85 parameter symbol conditions min max min max u nit write cycle time t wc 55 - 70 - ns chip enable to end of write t cw note 1 45 - 60 - ns address setup time t as note 2 0 - 0 - ns address valid to end of write t aw note 1 45 - 60 - ns write pulse width t wp note 1 40 - 5 0 - ns write recovery time (write cycle 1) t wr1 note 3 5 - 5 - ns write recovery time (write cycle 2) t wr2 note 3 15 - 15 - ns data valid to end of write t dw 20 - 25 - ns data hold time (write cycle 1) t dh1 note 4 0 - 0 - ns data hold time (write cycle 2) t dh2 note 4 0 - 0 - ns write enabled to output in high z t wz note 5 0 20 0 25 ns output active from end of write t ow note 5 5 - 5 - ns note: 1. a write ends at the earlier transition of /ce going high and /we going high. 2. a write occurs during the overlap of allow /ce and a low /we. a write begins at t he later transition of /ce going low and /we going low. 3. either t wr1 or t wr2 must be met. 4. either t dh1 or t dh2 must be met. 5. if /ce goes low simultaneously with /we going low or after /we going low, the outpu ts remain in high - impedance state. timing waveform - read cycle no.1 (address access)* 1,2 - read cycle no.2 (/ce access) *1,3,4 address d out data valid t oh t acc t rc previous data valid t ace t clz t rc t chz /ce high - z high - z d out
h anbit h m n128 8 j url: www.hbe.co.kr 6 hanbit electronics co.,ltd. re v.0.0 (february/ 2002) - read cycle no.3 (/oe access) *1,5 notes: 1. /we is held high for a read cycle. 2. d evice is continuously selected: /ce = /oe =v il . 3. address is valid prior to or coincident with /ce transition low. 4. /oe = v il . 5. device is continuously selected: /ce = v il - write cycle no.1 (/we - controlled) *1,2,3 t rc t ohz t oe t olz address d out /oe data valid high - z high - z t acc t wc t aw t as t cw t dw t wp t dh1 t wr1 t ow t wz data - in valid high - z data undefined (1) address d in d out /we /ce
h anbit h m n128 8 j url: www.hbe.co.kr 7 hanbit electronics co.,ltd. re v.0.0 (february/ 2002) address t wz t aw t cw t wp t wr2 t as t dw t dh2 high - z data undefined /ce d in d out /we data - in - write cycle no.2 (/ce - controlled) *1,2,3,4,5 note: 1. /ce or /we must be high during address transition. 2. because i/o may be active (/oe low) during this period, data input s ignals of opposite polarity to the outputs must not be applied. 3. if /oe is high, the i/o pins remain in a state of high impedance. 4. either t wr1 or t wr2 must be met. 5. either t dh1 or t dh2 must be met. power - down/power - up timing t pf /ce t wpt t fs t dr t pu t cer v so v pfd v pfd v so v cc 4.75 4.25
h anbit h m n128 8 j url: www.hbe.co.kr 8 hanbit electronics co.,ltd. re v.0.0 (february/ 2002) package dimension o r dering information h m n 1 28 8 j - 70 i unit : mm 24.52+/-0.2 2 3 . 5 0 + / - 0 . 2 1.50 1 . 5 0 1 . 2 7 10.82 13.31 3 . 0 5 . 6 3 5 device : 1 28 k x 8 bit speed options : 55 = 55 ns 70 = 70ns h anbit memory module nonvolatile sram jlcc type package operating temperature : i = industrial t emp. ( - 40~85 c ) blank = commercial temp. (0~70 c )
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